1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and, more particularly, to a semiconductor device made by a self-aligned suicide xe2x80x9csalicidexe2x80x9d technique wherein silicide films are formed on a gate electrode and a diffusion layer of a semiconductor device, and a manufacturing method thereof.
2. Description of the Related Art
In a salicide technique wherein a silicide film is formed in a self-aligned manner on a gate electrode and a diffusion layer of a semiconductor device, it is important that the silicide films have a low electronic resistance and are stable. Previously, a silicide technique using titanium (Ti) has been adopted. Titanium silicide film has a low specific-resistance and a suitable Schottky barrier height for both p-type and n-type silicon.
However, when using conventional methods of forming a Ti silicide film for making a finer semiconductor device, the following problem arises. The impurity concentration of the gate electrode and the surfaces of the diffusion layer increases as a pattern is made finer, which causes an increase in the phase transition temperature from titanium disilicide (TiSi2) of a C49 structure having a high resistance to titanium disilicide of a C54 structure having a low resistance, in the case of silicide overlying an n-type diffusion layer. Therefore, the difference between the phase transition temperature on the p-type silicon and the phase transition temperature on the n-type silicon increases.
Forming a Ti silicide film on an n-type diffusion layer therefore requires such high temperature that a pn-junction leakage characteristic is degraded and the silicide film on a p-type gate and the p-type diffusion layer is formed too thickly. On the contrary, when using the lower temperature necessary for forming a Ti silicide film on a p-type diffusion layer, the silicide film has a higher resistance due to insufficient silicidation and the heat resistance drops due to the resulting thin silicide film on the n-type diffusion layer. Accordingly, this conventional silicide film forming method is not sufficient as a technique for forming the silicide film on the gate electrode and the diffusion layer in a self-alignment manner.
In a paper of xe2x80x9cK. Goto et al., Technical Digest of IEEE International Electron Device Meeting 1995 (IEDM95), pp.449-pp.452 (1995)xe2x80x9d, there is disclosed a method wherein the silicide film is selectively formed on the gate electrode and the diffusion layer in a self-aligned manner by utilizing cobalt (Co) which has a smaller difference in silicide phase transition temperature as between the p-type silicon and n-type silicon, compared with Ti.
A conventional method of forming the silicide film is described with reference to FIGS. 3A to 3D. FIGS. 3A to 3D are schematic sectional views showing the steps of conventional silicide film forming method.
To start with, as shown in FIG. 3A, a MOSFET (metal oxide semiconductor field effect transistor) is formed in an element forming region defined by element isolation regions 102 on a silicon substrate 101. The MOSFET comprises gate oxide films 103, gate silicon films 104, sidewalls 105, and diffusion layers 106 having a n+/p junction depth of 100 nm, which are formed by a LOCOS (local oxidation of silicon) method.
As shown in FIG. 3B, a cobalt (Co) film 108 is formed on the MOSFET to a thickness of about 10 nm by sputtering. A titanium nitride (TiN) film 109 is formed on the Co film 108 to a thickness of about 30 nm by sputtering. The TiN film 109 is formed so as to prevent oxidation during the silicifying thermal treatment of the Co.
As shown in FIG. 3C, the silicon substrate 101 is subjected to a first thermal treatment at 550xc2x0 C. for 30 sec in a nitrogen atmosphere by a lamp rapid thermal annealing, thereby allowing surface portions of the gate silicon films 104 and the diffusion layers 106 to react with the Co film 108. Thus, a CoxSiy film 110 (where xxe2x89xa7y) is formed as a reacted layer of Co and Si on the gate silicon films 104 and the diffusion layers 106 in a self-aligned manner.
As shown in FIG. 3D, the TiN film 109 and that portion of the Co film 108 which remains unreacted on the element isolation region 102 and sidewalls 105, are removed by a wet etching method. After that, the silicon substrate 101 is subjected to a second thermal treatment at 550xc2x0 C. for 30 sec in a nitrogen atmosphere by a lamp rapid thermal annealing, thereby phase-transitioning the CoxSiy film 110 on the gate silicon films 104 and the diffusion layers 106 to a cobalt disilicide (CoSi2) film 111a which is thermally and compositionally stable and has a low resistance.
In this conventional method, cobalt is used as a silicide metal in place of titanium and the titanium nitride (TiN) film is formed on the cobalt film to prevent oxidation of Co upon the thermal treatment, thereby solving the problems of the silicide film having a high resistance and forming too thickly due to the higher phase transition temperature from the C49 structure titanium disilicide to the C54 structure titanium disilicide in the regions having a high impurity concentration.
However, in the conventional method, since the resulting silicide films have almost the same thicknesses on the gate and the diffusion layers, it has now been discovered that this causes the heat resistance of the silicide film on the gate electrode (consisting of polycrystalline silicon) to be lower than that of the silicide film formed on the diffusion layer (which is a single crystal), and the heat resistance of the device itself is thereby limited by the heat resistance of the silicide film on the gate. Although it would be advantageous simply to make the silicide film thick so as to improve the heat resistance, we have further discovered that this increased junction current leakage for diffusion layers having a shallow pn-junction.
Therefore, the object of the present invention is to solve the above problems.
In order to accomplish the object, according to a first aspect of the present invention, there is provided a semiconductor device having a gate electrode on a first region of a semiconductor substrate, a diffusion layer in a second region of the semiconductor substrate, a first silicide film on a surface of the gate electrode, and a second silicide film on a surface of the diffusion layer, wherein the first silicide film is thicker than the second silicide film.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising forming a gate electrode on a first region of a semiconductor substrate, forming a diffusion layer in a second region of the semiconductor substrate, forming a first silicide film and a second silicide film on the gate electrode and the diffusion layer, respectively, wherein the first silicide film is thicker than the second silicide film.
According to the present invention, based on the above constitution, since the thickness of the silicide film on the gate electrode is thicker than that on the diffusion layer, it is possible to improve the heat resistance of the silicide film on the gate electrode and also prevent the deterioration in the pn-junction leakage characteristic of the silicide film on the diffusion layer.